GateMate A2: High-Performance FPGA with 40k CPEs
COLOGNE CHIP Expands the GateMate Family
The GateMate A2 from COLOGNE CHIP is a new FPGA featuring twice the logic resources of the GateMate A1. Thanks to full pin compatibility, the GateMate A2 enables straightforward design upgrades with minimal hardware changes.
GateMate at a Glance
The GateMate family comprises two FPGA variants: the CCGM1A1 as the base version and the CCGM1A2, which consists of two CCGM1A1 dies in a single package. Die-to-die connections between the two dies of the CCGM1A2 link the routing structures together.
The GateMate A2 features 40k CPEs, equivalent to 80k 4-input functions. It includes two 5G SerDes interfaces and 64 blocks of RAM, with 40kbit per block. The FPGA also provides full support for an open-source toolchain based on Yosys and nextpnr.
Programmable Element Architecture
Each die features 20,480 programmable elements for combinational and sequential logic, 20,480 8-input LUT trees / 40,960 4-input LUT trees, and 40,960 latches / flip-flops within the programmable elements. Each programmable element can be configured as a 1-bit full adder, a 2-bit full adder, or a 2×2-bit multiplier. Dedicated logic and routing support fast arithmetic operations and multipliers of arbitrary size.
Flexible GPIO and I/O Connectivity
Each FPGA features 9 general-purpose input/output (GPIO) banks and 162 user-configurable GPIOs. All GPIOs can be configured as single-ended signals or LVDS differential pairs. The I/O cells include double-data-rate (DDR) registers, while all GPIOs are MIPI D-PHY compatible (CSI-2). The I/O voltage range is 1.2 to 2.5V.
Clock Generators and SerDes
Each die features four clock generators (PLLs) and supports a maximum oscillator frequency ranging from 1,000 to 2,500MHz. In addition, each die is equipped with a 5.0Gb/s serializer/deserializer (SerDes) interface.
Learn more about FPGA solutions.
What Are the Advantages of the GateMate A2 FPGA for Low-Power Applications?
The GateMate A2 from COLOGNE CHIP combines twice the logic resources of the A1 with full pin compatibility, 5G SerDes, extensive memory resources, and support for an open-source toolchain. Its architecture is particularly well suited for compact and energy-efficient FPGA solutions in low-power and cost-sensitive applications, for example in industrial control systems, embedded systems, and communication equipment.
Your Contact Person
Would you like to learn more about GateMate A2? Achim Stahl will be happy to advise you.
